(1) Field of the Invention
This invention relates to a semiconductor device verification system and a semiconductor device fabrication method and, more particularly, to a semiconductor device verification system for verifying layout data generated by the layout design of a semiconductor device and a semiconductor device fabrication method.
(2) Description of the Related Art
For example, the number of transistors included in large-scale integration (LSI) was about a thousand at first. With the progress of semiconductor technology, however, ten million to several hundred million transistors can be formed in LSI at present.
In addition, LSI design was made mainly by hand at first. However, there is a limit to design made by hand because of such a rise in the integration level of LSI. As a result, automatic design made not by hand but by a computer is used. In recent years an automatic design development tool called an electronic design automatic (EDA) is used for LSI design by a computer (see Japanese Patent Laid-Open Publication No. 2004-13264).
LSI design for which the EDA is used includes processes such as functional and logical design and layout design. LSI design for which the EDA is used will be described in brief.
First, in the functional and logical design a hardware description language (HDL) such as the Verilog-HDL is used for generating a logic circuit which meets the operation specifications of desired LSI. Whether the generated logic circuit is logically equal to the desired LSI described in the hardware description language is verified.
If no problem arises when the logic circuit generated by the functional and logical design is verified in this way, then layout design is performed on the logic circuit.
With LSI, transistors are formed by performing processes, such as epitaxial growth, ion implantation, ion diffusion, and etching, on a silicon wafer. When these transistors are formed, a mask corresponding to a treatment pattern is needed in each process. One mask is used in each process.
FIGS. 8 and 9 are schematic views showing a hierarchy of data for a chip layout.
In the layout design, as shown in FIGS. 8 and 9, a chip 100 is divided into small portions (cells) according to functional or logical unit instead of making a layout design for the entire chip 100. After each cell obtained by the division is located at an arbitrary position, cells are wired. By doing so, a layout is performed hierarchically. As a result, the layout of the chip 100 is performed and mask pattern data (layout data) used for fabricating the LSI is generated. The LSI is fabricated on the basis of the layout data.
After that, validity is checked from the viewpoint of fabrication. For example, whether the LSI is correctly fabricated on the basis of the layout data generated by the layout design and whether the LSI fabricated correctly functions are checked.
FIG. 10 is a schematic view showing a conventional physical verification system.
As shown in FIG. 10, whether layout data 201 generated by the layout design satisfies a standard rule for general LSI (design rule 202) is verified by the use of a physical verification system 205.
For example, the following case may occur. A static random access memory (SRAM) can actually be fabricated, but data which does not follow the design rule 202 is included. In this case, such data is set in advance in an excluded cell list 203 as an excluded cell. When verification is performed, the physical verification system 205 skips data included in the excluded cell list 203 of the layout data 201. As a result, a process is simplified by the amount of the data which the physical verification system 205 skips and verification efficiency rises.
The layout data 201 generated by the layout design is verified by the above verification method. Error data which is a verification result is outputted as a summary file 206. The contents of the error data depend on the physical verification system 205 used.
The physical verification system 205 is a design rule check (DRC) which verifies whether the layout data 201 generated satisfies the design rule 202, a layout versus schematic (LVS) which verifies whether the result of the layout design matches the result of circuit design, or the like.
The integration level of LSI is rising. Such LSI can efficiently be designed not by hand but by the EDA.
However, the physical verification system which performs a process by skipping the data included in the excluded cell list of the layout data has the following problems.
A process is simplified by skipping the data included in the excluded cell list. This is based on the premise that the data set as an excluded cell is not changed. Even if the data set as an excluded cell is changed, a process is performed by skipping the data. Accordingly, a change of the cell is not detected.
One of solutions for this problem is a layout versus layout (LVL). With this verification method, pattern matching of layout data generated by layout design and layout data for general LSI is performed to check that there is no differential between them. Of the layout data generated, a tier including an excluded cell and tiers lower than the tier including the excluded cell are usually verified in the case of the LVL. Therefore, if interference such as a wiring from the outside exists at a tier higher than the excluded cell, the interference cannot be detected.
It is necessary to wire each cell of a layout and the outside. Accordingly, each cell of the layout always suffers interference of some kind. However, the excluded cell is skipped when a process is performed. As a result, whether the interference which the excluded cell suffers from the outside is necessary is not checked.
One of solutions for this problem is to set an interference prohibition area in the excluded cell or to set a new design rule for detecting interference, for the purpose of checking whether the interference which the excluded cell suffers is necessary. However, if an interference prohibition area is set, the area of the layout increases, complexity increases because of, for example, a need to consider the achievement of a balance between the interference prohibition area and an interference permissible area, and the possibility of an increase in processing time and a deterioration in verification accuracy increases.
Furthermore, in a circuit information extraction process in which the LVS is used as a physical verification system, a method for designating a tier at which the extraction of circuit information compared with circuit information for general LSI begins traditionally exists. However, interference may occur between data corresponding to a tier higher than a designated cell and data corresponding to a tier at which extraction begins. In this case, the above method does not show which tier data that causes the interference belongs to. As a result, a processing method is indefinite and a user's purpose may not be realized.
In addition, if an element has, for example, a complicated shape, it is difficult to extract circuit information by a physical verification system in accordance with a conventional design rule. Wiring layers of an inductor are located so as to form a spiral. For example, if the LVS is used as a physical verification system, it is very difficult to extract the number of turns from layout data. If up-to-date technologies are used, information regarding various portions is extracted as parameters in order to increase accuracy with which various parameters of a transistor are extracted. However, it is very difficult to describe these parameters as a design rule and extract a matching result. If the DRC is used as a physical verification system, a cell for which a layout shape itself must be specified exists. For example, an analog element must have a specific shape from the viewpoints of a manufacturing yield and a characteristic assurance. However, a design rule is represented mainly by the minimum or maximum value of a pattern itself or a correlation. That is to say, a design rule is not suitable for specifying a shape itself. Therefore, it is very difficult to specify a shape by a design rule.
If various kinds of cells are located on one chip, design rules on these cells may differ from one another. In such a case, criteria for these design rules may interfere with one another. Moreover, there may be need to permit deviation from a design rule in a specific cell. In these cases, the setting of an excluded cell and interference which the excluded cell suffers must additionally be verified. As stated above, however, many problems arise if verification is conducted with the excluded cell taken into consideration.